hanbit hm d16m36m12eg url:www. hbe.co.kr hanbit electronics co.,ltd. rev.1.0(august.2002) - 1 - general description the HMD16M36M12EG is a 16m x 3 6 bit dynamic ram high - density memory module. the module consists of eight cmos 16m x 4bit drams in 32 - pin so j or tsop packages and four cmos 16mx1bit drams in soj or tsop packages mounted on a 72 - pin glass - epoxy substrate. a 0.1 or 0.22 uf decoupling capacitor is mounted on the printed circuit board for each dram components. the module is a single in - line memory module with edge connections and is intended for mounting in to 72 - pin edge connector so ckets. all module components may be powered from a single 5v dc power supply and all inputs and outputs are ttl - compatible. features w part identification HMD16M36M12EG - -- 4k cycles/64ms ref, gold w access times : 50, 60ns w high - density 64mbyte design w single + 5v 0.5v power supply w jedec standard pdpin & pinout w ttl compatible inputs and outputs w /cas - before - /ras & hidden refresh capability w /ras - only refresh capabil ity w edo mode operation option s marking w timing 50 n s access - 5 60 n s access - 6 w packages 72 - pin simm m performance range speed t rac t cac t rc 5 50ns 13ns 90ns 6 60ns 15ns 110ns presence detect pins (optional) pin 50ns 60ns pd1 vss vss pd2 nc nc pd3 vss nc pd4 vss nc pin symbol pin symbol pin symbol 1 vss 25 dq24 49 dq9 2 dq0 26 dq7 50 dq27 3 dq18 27 dq25 51 dq1 0 4 dq1 28 a7 52 dq28 5 dq19 29 a11 53 dq11 6 dq2 30 vcc 54 dq29 7 dq20 31 a8 55 dq12 8 dq3 32 a9 56 dq30 9 dq21 33 nc 57 dq13 10 vcc 34 /ras2 58 dq31 11 nc 35 dq26 59 vcc 12 a0 36 dq8 60 dq32 13 a1 37 dq17 61 dq14 14 a2 38 dq35 62 dq33 15 a3 3 9 vss 63 dq15 16 a4 40 /cas0 64 dq34 17 a5 41 /cas2 65 dq16 18 a6 42 /cas3 66 nc 19 a10 43 /cas1 67 pd1 20 dq4 44 /ras0 68 pd2 21 dq22 45 nc 69 pd3 22 dq5 46 nc 70 pd4 23 dq23 47 /w e 71 nc 24 dq6 48 nc 72 vss pin assignment 64mbyte (16mx36) edo/with parity mode 4k ref . 72pin - simm design part no. hm d16m36m12eg 72pin simm top view
hanbit hm d16m36m12eg url:www. hbe.co.kr hanbit electronics co.,ltd. rev.1.0(august.2002) - 2 - functional block dia gram /cas0 /ras0 /cas1 /w e a0 - a11 dq0 cas dq1 ras dq2 oe w a0 - a11 dq3 u0 dq0 cas dq1 ras dq2 oe w a0 - a11 dq3 u1 d cas q ras w a0 - a11 u2 dq0 cas dq1 ras dq2 oe w a0 - a11 dq3 u0 dq0 cas dq1 ras dq2 oe w a0 - a11 dq3 u1 d cas q ras w a0 - a11 u2 cas dq18 - dq21 ras oe w e a0 - a11 u7 cas dq22 - dq25 ras oe w e a0 - a11 u8 cas dq26 ras w e a0 - a11 u3 cas dq27 - dq30 ras oe w e a0 - a11 u11 cas dq31 - dq34 ras oe w e a0 - a11 u1 2 cas dq35 ras w e a0 - a11 u4 /cas 2 /ras2 /cas3 cas dq0 - dq3 ras oe w e a0 - a11 u 1 cas dq4 - dq7 ras oe w e a0 - a11 u 2 cas dq8 ras w e a0 - a11 u10 cas dq9 - dq12 ras oe w e a0 - a11 u5 cas dq13 - dq16 ras oe w e a0 - a11 u6 cas dq17 ras w e a0 - a11 u9 dq0 - dq35
hanbit hm d16m36m12eg url:www. hbe.co.kr hanbit electronics co.,ltd. rev.1.0(august.2002) - 3 - absolute maximum rat ings parameter symbol rating voltage on any pin relative to vss v in , out - 1v to 7.0v voltage on vcc supply relative to vss vcc - 1v to 7.0v power dissipation p d 12 w storage temperature t stg - 55 o c to 1 25 o c short circuit output current i os 50ma w permanent device damage may occur if " absolute maximum ratings" are exceede d. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc opera ting conditions ( voltage reference to v ss , t a =0 to 70 o c ) parameter symbol min typ . max unit supply voltage vcc 4.5 5.0 5.5 v ground vss 0 0 0 v input high voltage v ih 2.4 - vcc v input low voltage v il - 1.0 - 0.8 v dc and operating cha racteristics sy mbol speed min max units - 5 - 1080 ma i cc1 - 6 - 960 ma i cc2 don t care - 24 ma - 5 - 1080 ma i cc3 - 6 - 960 ma - 5 - 840 ma i cc4 - 6 - 600 ma i cc5 don t care - 12 ma - 5 - 1080 ma i cc6 - 6 - 960 ma i l(l) - 1 0 10 m a i o(l) don t care - 5 5 m a v oh 2.4 - v v ol - 0.4 v i cc1 : operating current * (/ras , /cas , address cycling @t rc =min.)
hanbit hm d16m36m12eg url:www. hbe.co.kr hanbit electronics co.,ltd. rev.1.0(august.2002) - 4 - i cc2 : standby current ( /ras=/cas=v ih ) i cc3 : /ras only refresh current * ( /cas=v ih , /ras, address cycling @t rc =min ) i cc4 : fast page mode current * (/ras=v il , /cas, address cycling @t pc =min ) i cc5 : standby current (/ras=/cas=vcc - 0.2v ) i cc6 : /cas - before - /ras refresh current * (/ras and /cas cycling @t rc =min ) i il : input leakage current (any input 0v v in 6.5v, all other pins not under test = 0v) i ol : out put leakage current (data out is disabled, 0v v out 5.5v v oh : output high voltage level (i oh = - 5ma ) v ol : output low voltage level (i ol = 4.2ma ) * note : i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are o btained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address cad be changed maximum once while /ras=v il . in i cc4 , address can be changed maximum once within one page mode cycle. capacitance ( t a =25 o c, vcc = 5v, f = 1mz ) description symbol min max units input capacitance (a0 - a11) c in1 - 50 pf input capacitance (/w) c in2 - 66 pf input capacitance (/ras0) c in3 - 38 pf input capacitance (/cas0 - /cas3) c in4 - 24 pf input/output capacitance (dq0 - 31) c dq1 - 17 pf ac characteristics ( 0 o c t a 70 o c , vcc = 5v 10%, see notes 1,2.) - 5 - 6 parameter symbol min max min max unit random read or write cycle time t rc 84 104 ns access time from /ras t rac 50 60 ns access time from /cas t cac 13 15 ns access time from column address t aa 25 30 ns /cas to output in low - z t clz 3 3 ns output buffer turn - off delay t off 3 13 3 15 ns transition time (rise and fall) t t 1 50 1 50 ns /ras precharge time t rp 30 40 ns /ras pulse width t ras 50 10k 60 10k ns /ras hold time t rsh 13 15 ns /cas hold time t csh 38 45 ns /cas pulse width t cas 8 10k 10 10k ns /ras to /cas delay time t rcd 20 37 20 45 ns
hanbit hm d16m36m12eg url:www. hbe.co.kr hanbit electronics co.,ltd. rev.1.0(august.2002) - 5 - /ras to column address delay time t rad 15 25 15 30 ns /cas to /ras precharge time t crp 5 5 ns row address set - up time t asr 0 0 ns row address hold time t rah 10 10 ns column address set - up time t asc 0 0 ns column address hold time t cah 8 10 ns column address hold referenced to /ras t ar 50 55 ns column address to /ras lead time t r al 25 30 ns read command set - up time t rcs 0 0 ns read command hold referenced to /cas t rch 0 0 ns read command hold referenced to /ras t rrh 0 0 ns write command hold time t wch 10 10 ns write command hold referenced to /ras t wcr 50 55 ns write command pulse width t wp 10 10 ns write command to /ras lead time t rwl 13 10 ns write command to /cas lead time t cwl 8 10 ns data - in set - up time t ds 0 0 ns data - in hold time t dh 8 10 ns data - in hold referenced to /ras t dhr 50 55 ns refresh period t ref 64 64 ns write command set - up time t wcs 0 0 ns /cas setup time (c - b - r refresh) t csr 5 5 ns /cas hold time (c - b - r refresh) t chr 10 10 ns /ras precharge to /cas hold time t rpc 5 5 ns access time from /cas precharge t cpa 2 8 35 ns fast page mode cycle time t pc 40 45 ns /cas precharge time (fast page) t cp 8 10 ns /ras pulse width (fast page ) t rasp 50 200k 60 200k ns /w to /ras precharge time(c - b - r refresh) t wrp 10 10 ns /w to /ras hold time (c - b - r refre sh) t wrh 10 10 ns /cas precharge(c - b - r counter test) t cpt 20 30 ns notes 1. an initial pause of 200 m s is required after power - up followed by any 8 /ras - only or /cas - before - /ras refresh cycles before proper device operation is achieved. 2. v ih (min) and v i l (max) are reference levels for measuring timing of input signals. transition times are measured between v ih(min) and v il(max) and are assumed to be 5ns for all inputs. 3. measured with a load equivalent to 2ttl loads and 100pf 4. operation within the t rcd(max) limit insures that t rac(max) can be met. t rcd(max) is specified as a reference point only. if t rcd
hanbit hm d16m36m12eg url:www. hbe.co.kr hanbit electronics co.,ltd. rev.1.0(august.2002) - 6 - is greater than the specified t rcd(max) limit, then access time is controlled exclusively by t cac . 5. assumes that t rcd 3 t rcd(max) 6. t ar , t wcr , t dhr are refe renced to t rad(max) 7.this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 8. t wcs , t rwd , t cwd anf t awd are non restrictive operating parameter. they are included in the data she et as electrical characteristic only. if t wcs 3 twcs(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. either t rch or t rrh must be satisfied for a read cycle. 10. these parameters are referenced to the /cas leading edge in early write cycles and to the /w leading edge in read - write cycles. 11. operation within the t rad(max) limit insures that t rac(max) can be met. t rad(max) is specified as a reference point only. if t rad is greater than the specified t rad(max) limit. then access time is controlled by t aa .
hanbit hm d16m36m12eg url:www. hbe.co.kr hanbit electronics co.,ltd. rev.1.0(august.2002) - 7 - packaging informatio n simm design unit : mm o r dering information part number density org. package ref . vcc mode speed HMD16M36M12EG - 5 64mbyte x 36 72 pin - simm - gold 4k 5v edo/ parity 50ns HMD16M36M12EG - 6 64mbyte x 36 72 pin - simm - gold 4k 5v edo/ parity 60ns 6.35 0.2 2 7.0 0.2 1.27 0.2 3.34 0.2 2.03 0.2 1.0 0.2 6.35 0.2 95.25 0.2 10 7 .9 5 0.20 3.38 0.2 6.35 0.2 10.16 0.2 71 1 3.38 0.2 < front view > 0.2 5 max min 2.54 1.27 gold : 1.04 0. 10 solder:0.914 0.10 1.2 7
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